15 Dec
2008
15 Dec
'08
7:44 p.m.
bfranchuk at jetnet.ab.ca wrote:
der Mouse wrote:
The idea of a RISC is that out of few general addressing modes
( to keep decoding simple ) you generate all the other needed
ones in software. Since decoding is so simple you can ran faster by
pipelining
everything and goes real fast, providing *gotya* main memory is that fast
too.
But again, none of those performance enhancement strategies are
*required* to be in a RISC chip.
Peace... Sridhar
How do
you have RISC from a CPLD since RISC implies a large register
stack?
It does? I thought it implied a (moderately) minimalist instruction
set. This tends to correlate with having lots of registers, but that's
hardly necessary - consider the PDP-8, for example.