TTL 7400's Available

woodelf wrote: If the difficulty with flip-flops is coming up with an edge-triggerred design, or regardless, you might be interested in a scheme used in (many) Japanese SSI calculators from the late 60s: - All flips flops are a master-slave form, but each section (M & S) is a basic, dead-simple, gated flip-flop. - The clock presents two phases to the system, the phases being *non-overlapping* pulses. - All slave sections are gated *directly* by one phase of the clock (call it the update phase). - Master sections are gated by the other phase (call it the capture phase), but not (necessarily) directly: typically, intervening logic controls whether a given master section is gated or not, as per the desired function of the flip-flop. Because the slave section outputs are all modified simultaneously, but asynchronous to the master sections, the master section inputs are guaranteed to be stable when the master sections are gated (as long as the longest logic propagation path is accounted for). Advantages: - simple flip-flop design, no need for edge-triggerring. - no concern about setup or hold times. - fully synchronous at the system level, no worrying about propagation glitches, etc. Disadvantages: - every 'system flip-flop' or 'bit of state' is actually two (gated) flip-flops. (Another cheap trick in the SSI IC era was to front a basic 2-gate flip-flop with discrete capacitors and resistors to get edge triggerring.)