18 Apr
2000
18 Apr
'00
10:13 a.m.
please see embedded comments below.
Dick
----- Original Message -----
From: <allisonp(a)world.std.com>
To: <classiccmp(a)classiccmp.org>
Sent: Tuesday, April 18, 2000 7:33 AM
Subject: Re: 8-bit IDE
On Mon, 17 Apr 2000, Richard Erlacher wrote:
> My experience with Q-Bus I/O was always spoon-fed via a DRV11-WA card.
That
<snip>
Qbus output address at Bsync/ (like 8085 ALE) and you latch the address
off the databus, plus BBS7 (bankselect 7 is the IOpage) and theres your
address. The next part of the cycle is typically an IO_read with an
optional IO_write to follow. What makes doing IDE on PDP11 is the read
before write to the same address (plays havoc with device resgisters).
the simple solution is to map all reads to base+0 to base+n and writes
to base+N to Base+n+n so reads do not overlap writes.
So you'd advocate essentially using the Write signal (forgive me if I
don't
remember which name that one wore) as an address line, kind of like the
AMPRO folks did on their FDC?
Allison