22 Feb
2006
22 Feb
'06
8:46 p.m.
Don North wrote:
I added the suggested test case 196607./3. to the DIV
test, and here
are the
results from both SIMH and the 11/44. The suggested behavior above
does not
hold true. In both instances for this test case (the second lines) the
result
registers are unchanged, and the V-bit is set. The quotient result is not
the low 16b of the 32b quotient, but is the source register unaltered.
Here's the result from SIMH:
local[516] pdp11 divtest.ini
PDP-11 simulator V3.5-0
DIV Test of 'div r2,r0'
..R0.. ..R1.. ..R2.. ....NUM... ..DEN.. => ..R0.. ..R1.. ..R2.. NZVC
..QUO.. ..REM..
000003 000004 000003 196612. 3. => 000003 000004 000003
0010 3. 4.
000002 177777 000003 196607. 3. => 000002 177777 000003
0010 2. -1. <---
000000 000000 000000 0. 0. => 000000 000000 000000
0111 0. 0.
000001 000001 000000 65537. 0. => 000001 000001 000000
0111 1. 1.
000000 001000 000010 512. 8. => 000100 000000 000010
0000 64. 0.
000000 001234 000021 668. 17. => 000047 000005 000021
0000 39. 5.
000010 001234 005432 524956. 2842. => 000270 003754 005432
0000 184. 2028.
012345 012345 054321 350557413. 22737. => 036071 051134 054321 0000
15417. 21084.
012345 012345 000005 350557413. 5. => 012345 012345 000005
0010 5349. 5349.
000000 040000 000002 16384. 2. => 020000 000000 000002
0000 8192. 0.
000000 100000 000002 32768. 2. => 040000 000000 000002 0000
16384. 0.
000001 000000 000002 65536. 2. => 000001 000000 000002
0010 1. 0.
000002 000000 000002 131072. 2. => 000002 000000 000002
0010 2. 0.
Goodbye
HALT instruction, PC: 000010 (000012)
Goodbye
local[517]
and here's the result from a real PDP-11/44:
Jerome Fine replies:
I also did similar tests again on the PDP-11/73.
Specifically, a KDJ11-AB (M8192-YB) board. I would
imagine that all of the J-11 chips are the same.
I thought that I had different results the last time,
but I did not write them down and my memory was not
correct. This time I checked exactly and when the
quotient result is supposed to be > 32767., the
overflow bit is set and the registers are unchanged.
The subroutine that takes advantage of E11's results
uses BASE 10000 values to ENCODE a 512 byte variable
(32 words of 16 bits). Each of the 32 words has its
own entry consisting of up to 40 BASE 10000 values
which are easily calculated as required using the
values from the entry for the previous word. The code
simply does a multiply by 65536 (actually just a word
shift) and a divide by 10000. to each value in the
entry and carries the overflow up the values. Anyone
who wants more details, please ask. For example, the
first three entries (a zero specifies the end of the
entry) are:
1, 0 = 2**0
5536, 6, 0 = 2**16
7296, 9496, 42, 0 = 2**32
Obviously, no value can be larger than 9999., but
even then, an overflow will occur - UNLESS I first
subtract 327680000. from the dividend (or 5000.
>s 1000
(Program)
DIV Test of 'div r2,r0'
..R0.. ..R1.. ..R2.. ....NUM... ..DEN.. => ..R0.. ..R1.. ..R2.. NZVC
..QUO.. ..REM..
000003 000004 000003 196612. 3. => 000003 000004 000003
0010 3. 4.
000002 177777 000003 196607. 3. => 000002 177777 000003
0010 2. -1. <---
000000 000000 000000 0. 0. => 000000 000000 000000
0011 0. 0.
000001 000001 000000 65537. 0. => 000001 000001 000000
0011 1. 1.
000000 001000 000010 512. 8. => 000100 000000 000010
0000 64. 0.
000000 001234 000021 668. 17. => 000047 000005 000021
0000 39. 5.
000010 001234 005432 524956. 2842. => 000270 003754 005432
0000 184. 2028.
012345 012345 054321 350557413. 22737. => 036071 051134 054321 0000
15417. 21084.
012345 012345 000005 350557413. 5. => 012345 012345 000005
0010 5349. 5349.
000000 040000 000002 16384. 2. => 020000 000000 000002
0000 8192. 0.
000000 100000 000002 32768. 2. => 040000 000000 000002 0000
16384. 0.
000001 000000 000002 65536. 2. => 100000 000000 000002 0010
-32768. 0.
000002 000000 000002 131072. 2. => 000002 000000 000002
0010 2. 0.
Goodbye
(Console)
Halted at 165146 from the high order word). Since I need only 6 extra
instructions to handle the problem, it seems worthwhile
to do so(* is for an extra instruction):
Clr -(SP) ;* Set flag value for no overflow
Cmp #4999.,R2 ;* Branch if no overflow will
Bhis 10$ ;* occur on the divide
; Sec ;* Carry bit is already set
Ror (SP) ;* Set up extra 32768. for quotient
Sub #5000.,R2 ;* Remove excess dividend
10$:
Div #10000.,R2 ; Perform the divide without overflow
Add (SP)+,R2 ;* Increment quotient by 32768. as required
Can anyone suggest a better solution?
NOTE that the above solution is VERY specific to the
values that can be generated in this specific situation.
Thank you to Don North and Johnny for your interest!
Sincerely yours,
Jerome Fine
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