14 Jul
2015
14 Jul
'15
10:21 p.m.
My experience
of FPGAs is that if you design a circuit for an FPGA it will work. If you take an existing
design
feed it into a schematic capture program and compile it for an FPGA then it won't.
Actually, you can, and I have done so - provided that the original
machine was slow enough. It works, in part, because the FPGA's are
sooooooooooo much faster than the original design, that you can use the
"trailing D flip flop" approach I described to convert the former into
the latter - the glitches occur on the time scale of the FPGA logic, but
are gone by the time the next simulated machine clock arrives.