11 Dec
2003
11 Dec
'03
8:42 a.m.
Eric Smith wrote:
The minimum write data pulse width spec for the WD1000
controller
is 60 ns. If we were sampling and reconstructing a sine wave with
a 120 ns period, 16.7 MHz sampling would be adequate. But that
wouldn't yield good results for square waves, and there wouldn't be
any margins. In practice, I suspect that 33.3 MHz sampling would be
barely adequate provided that no other problems arise. Operating at
50 MHz seems advisable to have reasonable margins.
Remember only the leading edge is important so this just digital data.
While you need a high clock to reduce jitter, remember too about
meta-stable problems. When you think about it you would only need about
say 4 bits of information per
data clock. 1 bit would be pulse yes/no and the other 3 bits would be
phase shift from the master clock. Now do you really need to use a FPGA
when a PAL's might be better with external ram.