28 Nov
2008
28 Nov
'08
8:54 a.m.
What is the minimum satisfactory sampling rate if one
wanted to emulate an ST-412
interface and have it RLL (2,7)-capable?
2x, assuming you regenerate the clock. With a digital DLL, the incoming clock would
be on the order of 8x the maximum incoming frequency.
The bitstream is not variable frequency. You can think of what is needed as the inverse
of the read recovery circuit on the drive controller.
The tricky part is generating the recirculating bit stream that you send as read data
back from the simulated drive. It is expecting the data that it just wrote to be in
the data read back on the next revolution. And you need one of these bitstreams for each
head.