1 Apr
2022
1 Apr
'22
5:32 p.m.
On Apr 1, 2022, at 5:13 PM, Brent Hilpert via cctalk
<cctalk at classiccmp.org> wrote:
On 2022-Apr-01, at 11:51 AM, Paul Koning wrote:
Maybe I'm being overly cautious, but offhand I'm initially skeptical without
doing the math or some good vector diagrams, or seeing an example. With the diagonal wire
you're changing the current/magnetic sum vectors in direction and magnitude. The
question is coming up with a current that reliably performs the cancellation function on
the selected core of a bit-array while reliably *not* selecting another core, while
accounting for all the variation tolerances in the array.
While there's probably some value by which it would work in theory, I wonder whether
the diagonal wire would narrow the operating margins. From some stuff I've seen, the
hysteresis curves for cores weren't spectacularly square. With the usual 3D-3wire
scheme of a close parallel inhibit wire you have 'cancellation by simplicity', you
maximise the difference (cancellation) influence on one wire while minimising it's sum
influence on the other.
A related issue is the normal diagonal sense stringing (which this looks to have) has the
wire entering the cores from both directions relative to the address wires, which is why
sense amplifiers respond to pulses of both polarity. If this diagonal wire is put to use
as an inhibit wire, some logic is needed to decide the direction of the inhibit current
from the address, though that may not be very difficult.
You're right about the diagonal wiring, that suggests the idea isn't very
practical. I suppose another possibility for a 3-wire core plane is that it's
linear-select with inhibit (as, for example, in CDC 6000 series ECS, extended core
storage).
Speaking of CDC and inhibit, the CDC mainframe memories (12 bit by 4k modules) are
peculiar in that they have inhibit wire pairs, one X and one Y, and four of them in each
direction so a given inhibit acts on a 1/16th square of the full plane. The best reason I
can figure for this is to have the number of cores traversed by the inhibit wires and by
the address wires to be roughly the same, so the inductance is fairly consistent and a
single design of ultra high speed current pulse drivers will work for all of them. The
drivers used are current diversion drivers -- they don't switch on and off, instead
they switch the current from an idling path to the core wire. It's pretty wild stuff,
one of the 6600 training manuals describes it in a lot of detail. My assumption is that
all this was done to achieve the unusually high speed: 1 microsecond full read/restore
cycle in 1964.
paul
On Apr 1,
2022, at 2:38 PM, Brent Hilpert via cctalk <cctalk at classiccmp.org> wrote:
On 2022-Apr-01, at 6:02 AM, Paul Koning via cctalk wrote:
I wonder if the sense wire was used as inhibit during write cycles -- that seems doable.
It would make the core plane simpler at the expense of more complex electronics. With
that approach, you have regular memory, not limited to 1 bit words. When I looked at that ebay listing of "glass
memory" it pointed me to another item,https://www.ebay.com/itm/265623663142 --
described as "core rope memory". Obviously it isn't -- it's
conventional core RAM. Interestingly enough, it seems to be three-wire memory (no inhibit
line that I can see). It looks to be in decent shape. No manufacturer marks, and
"GC-6" doesn't ring any bells.
Well, it would still work for 1-bit-wide words, so to speak. One wonders what the
application was.