IDE <-> MFM

Al Kossow wrote: An FPGA with a big shift register inside? Or just use some on-chip RAM (e.g. BlockRAM), a counter and a pair of 8-bit shift registers (two means you can load one while the other is shifting, and eliminate any stream discontinuities caused by the shifter reloading). It's not like SRs are particularly chip-intensive... Or you could go with a board full of TTL.... Based on a quick look at the ST506/412 OEM manual (it's on bitsavers -- thanks Al!) you're basically talking about a floppy disc data separator tweaked to run at a higher clock rate... Store a "1" if there was a flux transition in a given bit cell, or store a "0" if there wasn't. Head-switching would be a total pig unless you buffered all 8 (or 16) heads at once. 8us is not enough to ping an external IDE HDD (or say a CompactFlash or SD card) and read off an entire track of data... I don't even know how you'd be able to lock a PLL against the write data stream quickly enough not to make a hash of it. Most data separators (or at least the ones I've looked at) need a few bytes worth of encoded data to lock onto before the data window signal is actually valid... I suppose you could do what the Catweasel does and save the time between flux transitions, but that opens up a whole other can of worms when you want to write back to the disc... -- Phil. philpem at philpem.me.uk http://www.philpem.me.uk/