ST-506 hard drive emulation

On 7/26/05, Tony Duell <ard at p850ug1.demon.co.uk> wrote: Are you sure about that 50 MHz? I would have guessed 10 MHz would be fast enough. Um, wouldn't you use each bit in a word as a different head rather than than address bits withing a word? It's not like you can't perform an SRAM read+write cycle in 20 ns, although direct to [S]DRAM might be a bit more challenging. So in terms of 50 MHz sampling, you're talking 1 Mbit per head of fast memory for cylinder cache (you might as well choose a multiple of 8 heads), 1Mbit per head per cylinder of slow non-volatile memory for storage, and a PIC to transfer between the two (handle the "stepping") and a FPGA to hold the logic (a resettable 50 MHz, 20 bit counter tristated to the cache address bus and the read/write logic) So a 20 MB drive (8*640*17) is 1 MByte of fast memory, and 640 MB CF card. If 10 MHz is fast enough you can reduce those memory requirements by a factor of 5. Sounds like fun. :) Wish I had the time... Eric