18 Jun
2011
18 Jun
'11
11:55 a.m.
On 2011 Jun 17, at 10:59 PM, Chuck Guzis wrote:
On 18 Jun 2011 at 1:27, Dan Roganti wrote:
When I reverse engineer old equipment (discrete or early SSI where the
ICs also have to be decoded) I have to decide whether some collection
of components or the object in some black-box IC is a (N)AND or (N)OR
gate. As I work through the system I assess what makes the most sense
for the overall design. Sometimes it is fairly obvious, for example
when the system is built from a lot of structures of the form
gateTypeA ==> gateTypeB ==> inverter
you can bet it's AND-OR-INVERT, not OR-AND-INVERT.
I then carefully specify the logic levels for the system, e.g.:
Gates are drawn with Logic 0/false = 0V, Logic 1/true = -10V.
I find that's really all that is needed.
I actually try to stay away from the terms negative and positive logic
as they have always struck me as somewhat ambiguous, I've never really
seen a rigorous description. Rhetorically, are we talking about:
- voltage levels? (+5 > 0)
- magnitude of voltage levels? ABS(-10) > 0.
- 'logic' level? (0 is 'more negative' than 1)?
- high vs low? (higher as it appears on a scope face? but
logic 1 is 'higher' than logic 0 even if 1=0V & 0=+5V)
- assertion level?
- what if signals are named using false assertion levels, where
false is a more positive voltage then true?
- etc.
I have a schematic from the 60's that used, in essence, 4 types of gate
symbols: one each for +/- AND/OR, but you still have to scratch your
head some when it comes to interpreting signal levels at the different
types of gates.
hope my ascii schematics still works (using
courier font)
Maybe we're saying the same thing and not seeing it.
Positive logic
AB --DeMorgan-> ~((~A) + (~B))
To negative logic, drop the bubbles on the DeMorgan equivalence on
inputs and outputs. To avoid confusion, we'll say that the logic
gates retain their same operation for high (H) and low (L) voltages:
AB (postive logic) = (A+B) negative logic
LL L LL L
LH L LH H
HL L HL H
HH H HH H
If, in the first colum, we take H = 1 and L = 0, and in the second
column, H = 0 and L = 1, the logic maps are identical.