17 Jun
2011
17 Jun
'11
11:12 p.m.
On 18 Jun 2011 at 5:17, Alexey Toptygin wrote:
By 'not glitchless' do you mean that if you
simultaneously change the
inputs from 00 to 11 you'll see an approx. 1 gate delay wide transient
on the output of the XOR due to some of the signals passing through 2
and some through 3 NANDs?
Yes.
Is there a way to build an XOR from other types of
gates that won't
glitch on any of the input transitions 00 <-> 11 or 10 <-> 01 ? Even
if you can't guarantee that all the gate delays are the same?
You could at the simplest, add a 1 unit delay (buffer) on the A and B
lines in parallel with the first NAND gate.
--Chuck