Differentiating chips (Was: Newbie member saying something!!!

Well, check at startup the DX register - if DH is 3 it is a DX, if 23 it's a SX (DL is the stepping). No idea about if the moving thing is a possible test, only the difference in the results is quite low - you have to compare speed differences between instruction timings of known instruction sequences. The biggest Backdraft on the early SX was, if I remember correctly, that the BIU did always do 32 bit transfers, no matter if the requestes data was 8, 16 or 32 Bit and a worst case miss alignd 16 bit access (i.e. on address ...11) would result in two 32 Bit accesses which eventualy became 4 16 Bit data transfers. But as I said, this applied AFAIR only to early SXes - and of course not to all second source SX. So the only test I can imagine right now is the weak test thru using the Memory space - Switch the CPU to Flat addressing, and check for example if the BIOS ROM is mirrored every 16 MB (or if it is only mirrored every 64 MB, which gives you a CX CPU). Just if the board designer did only include 24 (or 26) address lines, your test will still fails, even on a DX :(. I cant think of another 'legal' way other than pushing Reset and checking DH (and later on checking the Type instruction of the CX core) Anyways - maybe check also a nice Dr.Dobbs article about AP485 and some blockheads at Intel (I may add that in the 286 Manual they described safer tests :) http://www.ddj.com/articles/1996/9609/9609o/9609o.htm Gruss H. -- Stimm gegen SPAM: http://www.politik-digital.de/spam/de/ Vote against SPAM: http://www.politik-digital.de/spam/en/ Votez contre le SPAM: http://www.politik-digital.de/spam/fr/ Ich denke, also bin ich, also gut HRK