7 Feb
2010
7 Feb
'10
7:56 p.m.
On Feb 7, 2010, at 5:36 PM, Ben wrote:
See: CPLD design. This current design is CPLD/2901 bitslice design.
The ALU is 12 bits, double clocked to give a 24 bit CPU on a 6800/6502
style memory cycle.One CPLD is for high speed decoding and the other
for the MAR and MBR data paths. A 8 bit refresh counter is for
DRAM's. A 2.5 MHZ (top speed)clock gives a 800 ns memory cycle. 3
2901's make
up the data path.
That sounds like fun.
Had you ever thought about making boards for these to sell to
people? I'd want a couple, I'll bet some other people would buy them
too...they sound like fun to hack on.
-Dave
--
Dave McGuire
Port Charlotte, FL
PS. I have a design concept with about the same number
of gates as
6809 or a Z80.
Cool! Describe?