25 Aug
2005
25 Aug
'05
11:31 a.m.
From: "Richard A. Cini" <rcini at
optonline.net>
All:
I have to say that I'm nearly ready to throw this 8800b through a
window. I purchased, yet again, another memory board in an effort to
nail-down some stable memory for this system and reach 48k with the fewest
boards possible. I've got the system booting BASIC with 16k, but I want
more.
This board is a 64k Central Data Systems DRAM card. I confirmed that
it was strapped properly for an 8080-based system (sets refresh rate, etc.).
This time I get problem I've never seen before.
On RESET, the data LEDs show 0xff. If you toggle a value and DEPOSIT
it, it will usually store but the LEDs will still show 0xff. If you EXAMINE
the location, it will show the right value.
Hi
It sounds like a timing problem. It might be that the CPU isn't
recognizing the wait states or something. Still, it sounds like it
is excepting the value. You don't have similar problems with
other memory boards?
Does it still retain the value, if you go to another location
first and then return? If so, I'd say it was a working board.
It might be just a feature of the DRAM controller chip that it
doesn't allow access to a location just written on the next cycle.
If you toggle in a short piece of code does it execute the code
or does it just go off to never never land? It might also be
some type of buss contention.
As I recall, any time you are looking at a specific location, the
front panel generates a JMP xxxx, where the xxxx is the front panel
switches. As I recall, any examine next or deposit next operation
uses the NOP to point to the next location.
You might check to see how the address lines look right after
the deposit. As I recall, they should be static with the address
of the last location referenced by the front panel. I don't have
a schematic handy so I'm not sure. It might be that the front
panel is doing something funny with the deposit. It might
be doing a deposit next or something.
Anyway, gather some more symptoms?
Dwight