18 Dec
2008
18 Dec
'08
9:39 p.m.
Vincent Slyngstad wrote:
I'm hoping to get around that by declaring
TP1...TP4 (and *strobe*, etc.)
to be the clocks, and re-expressing the latches so that they are clocked
by an "official" clock. I don't know yet how well that is working out,
as it's buried in with the other 188 warnings-of-the-moment.
First goal get it working ... That is why I am staying away from doing a PDP -??
with CPLD's, I don't have all the knowlage up keeping the same features and
bugs as the original hardware.
Vince
Sometime late January, I hope to have the logic for a 20 bit cpu using 5 CPLD's,
I find them a little more DIY freindly than FPGA's. Expect to have ballpark
PDP-8/e
speeds with but I have run with .8 us static ram memory cycle because I can't use
the trick the PDP-8 uses for address generation, but run address generation
thru the main adder. That is the price you pay for modern features like a Stack
pointer
or Index register. The fun part here is just having I/O pins just to display
the AC, Mar and data
from the last memory cycle, and a Switch register. Good
luck with your design
on those features.
Ben