How were 32-bit minis built in the 70s/80?

The VAX 730 was built with 2901s. DEC used 2901s in other places too; the UDA50 was built that way (2901 with 2910 sequencer). They had a custom assembler with two opcodes per line, one for the ALU and one for the sequencer. The condition codes were those from the preceding instruction, not the current ALU instruction, so you could see oddball stuff like this: clr r0; bne foo A bit like branch delay slot programming in MIPS... On the subject of custom chips: DEC used gate arrays a lot. For example there is the Pro 380 in which much of the discrete chip logic from the Pro 350 has been absorbed into one or two gate arrays, with all the unnecessary flexibility of the original chips omitted. Those were CMOS I believe. The Western Research Lab (in Palo Alto, down the road from Stanford) had a project somewhat later to build VLSI full-custom designs in ECL. They built a whole set of design tools that were very clever, allowing mixing of description anywhere from geometry to C-like programs. And the actual layout generation was rule-based so they could switch to a different factory that used different design rules with pretty much just a recompilation of the design. They needed that; there were a number of ECL fabs at the time but they were all shutting down. They designed a 1 GHz Alpha, and/or MIPS, and built a number of test chips but I don't know that a complete CPU was ever made. They also did early work on how to power and cool high powered chips; those designs ran over 100 watts which at the time was utterly unheard of. There are some internal tech reports documenting this work; I don't know that any of it was ever published outside. paul