On 1/30/2022 2:56 PM, Glen Slick via cctalk wrote:
On Sun, Jan 30, 2022 at 11:43 AM Chris Zach via
cctalk
<cctalk at classiccmp.org> wrote:
From the books, the kmc11 had an "lsi11 on board", 1k of 16 bit ram, 1k
of 8 bit data memory a 300ns cycle time, 16 bit microprossor with a 16
bit micro-instruction bus and 8 bit data path. This is according to the
1980 Terminal and Communications handbook, so it's a few years after the
1976 timeframe of Sha Tin.
Now the original LSI11 processor was 4 main chips, an EIS/FIS chip (or
the CIS lite chip or the weird 1k*20 bit micro-ram board which I have
somewhere). The DCT11 was a single chip lsi11 that had an 8 or 16 bit
outside bus and a 16 bit internal structure and ran pdp11 instructions.
So the KMC11 probably had the DCT11 chip.
The LSI11 chipset was around in 1975, so it makes sense that DEC could
use it. The SBC11/21 came out in 1981 but the chip was probably avail
internally by 1980 so I'm guessing that the KMC11 and the COMM-IO-DP was
using the DCT11.
http://www.bitsavers.org/pdf/dec/unibus/MP01118_KMC11B_EngrDrws.pdf
KMC11-B Field Maintenance Print Set
The KMC11-B used a custom bit-slice processor implementation.
(3x) 93S16 4-bit counters for a 12-bit program counter
(2x) 74S181 4-bit ALUs for an 8-bit ALU
(2x) 74S189 16x4 RAM for 16 8-bit working registers
If anybody has any schematics for the KMC11 (not the B version), I'd
love to get a copy of them.
The KMC11 and the KMC11-B are relatively incompatible with each other.
The KMC11-B has 4x more data memory, has 4x more microcode memory, and
loads microcode in a completely different way.
I have a KMC11 implementation in my KS10 FPGA, but it's implementation
is based on guesses and reverse engineering the diagnostics.
Thanks in advance.
Rob Doyle.