4 Nov
2005
4 Nov
'05
1:36 a.m.
On 11/3/2005 at 6:22 PM ard at p850ug1.demon.co.uk wrote:
Oh come on. It's broken. Fundamentally.
For one thing you can't arbitratily set the direction of individual port
lines (virtually all other parallel chips let you do that). And that
write-to-mode-register-clears-outputs is ridiculous.
Even at the time it was designed the latter should have been realised to
be a very bad idea. In fact I still wonder why they did it (setting all
outputs high would have been mildly more sensible).
The worst, by far, has to tbe the 8255 parallel
chip. That was clearly
designed by soembody who didn't think what he was doing. For those of you
who've not read the data sheets, any write to the mode control register
clears all output port lines to 0.
For what it is and WHEN it was developed, the 8255 is a pretty good device. There are still new products made that use it (very
popular in the data
acquisition area). I can't think of any other single parallel interface
I suspect only because it was trivial to link to the ISA bus. Linking up
a 6821 (approximate contemporary) was more work.
chip from the 70's that's still puffing
along.
I wish the thing was faster. The NEC 82C55AC variant is good to 10 Mhz,
but that's pretty slow when you're talking about a PCI bus.
There are precious few of the really good peripheral chips from the early
days of the microprocessor that are still as useful. The Signetics 2651
USART, maybe?
I can think of plenty that would be more useful if they were still being
made. The 6522 would come high up the list.
-tony