29 Jan
2009
29 Jan
'09
2:34 p.m.
ISTR someone asked why higher-capacity chips take
longer to erase.
Newer chips use smaller transistors -- the smaller the transistors,
the smaller the "floating gate" is, and the less SiO2 there is to be
hit by the UV. Less area = less energy absorbed
True, but...
= less charge leakage = longer erase time.
I'm not convinced. Less area = smaller floating gate = less charge to
leak, too; it seems to me that UV flux per nm^2 and the thickness of
the oxide would be the relevant variables, not the area of the floating
gate per se.
Or do you have some hard reference for this? It's not clear whether
you're repeating something you found in an authoritative source or an
"it sounds reasonable to me" or "somebody told me" or what.
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