29 Apr
2013
29 Apr
'13
3:39 p.m.
On 04/29/2013 08:59 AM, David Riley wrote:
Yes, the static timing analyzers are really built for synchronous
designs. You can do asynchronous logic with glitches, but you
then have to carry a strobe with you, which almost defeats the
point. There's an FPGA company called Achronix whose first FPGA
offerings claimed to be reaping the benefits of clockless logic,
but I don't see that anywhere in their literature now (their name
still belies their origins, though).
Is this an accidental a cross-post from the FPGA-SIMH discussion? If
not, I can't figure out how the subject of block-addressable tape swung
around to embrace the subject of clockless logic.
Wasn't the Philco System 2000 an asynchronous system? And weren't there
certain bipolar multipliers (TRW?) that operated clocklessly and had a
"done" status line?
Just trying to remember.
--Chuck