25 Oct
2012
25 Oct
'12
12:36 p.m.
On Oct 25, 2012, at 12:05, Chris Elmquist <chrise at pobox.com> wrote:
Wondering if you are considering the voltage level
translations to
modern FPGA and micros in whatever transceiver scheme is selected too?
ie, if we put down 3.3V or 1.8V modern parts, how do we get to/from the
5V domain on the backplane?
Certainly. The bright side is that 3.3v drives TTL inputs
(which typically have a Vih of 2v or so) just fine. If our FPGA/
CPLD is running 3.3v I/O, we're set as far as driving out.
Input is a little more shaky, since all the comparators I've
specified here have TTL outputs as well, which means
a typical Voh of 3.5v. That's still within the maximum limits
of most 3.3v input stages on FPGAs, and they often have
protection diodes which kick in above 3.6v (largely for
reflected-wave switching buses like PCI where you're just
about guaranteed excursions above 3.3v). They can
typically absorb a few mA each, and the TTL outputs
of these comparators don't drove high more than about
100 uA. So we should be good on the interfacing.
I've definitely used the AVC family parts for CMOS voltage
level translation, where it really matters because CMOS
drives hard in both directions almost rail to rail. My personal
"favorite" was a TI DSP that didn't have any I/O voltage
EXCEPT 1.8v, which meant we had to use those to
talk to nearly every peripheral on the board.
Since I don't see any reason to put down anything
other than 3.3v parts for the FPGA/micro, I
think we ought to be set.
- Dave