On 03.01.2014 19:57, Rob Doyle wrote:
Not to start a flame war, but it is my personal
belief that someone just
getting started with HDLs should strongly consider VHDL.
Oh, this *is* worth a (little and friendly) flame war.
Its strong type-checking forces you to think
about (and understand)
signal types and type conversions.
Oh yes! And having a typo in a signal name does not result in silently
having a new unconnected signal. And implicitely assigning something to
something that does not fit - just does not work.
Exactly.
The compiler directive (i.e., kludge added in later versions of verilog) ...
`default_nettype none
... will fix one of those issues, at least.
Rob.