How do they make Verilog code for unknown ICs?

Verilog and VHDL are two "hardware description languages". You can think of them as programming languages to describe hardware behavior. Another way to look at them is as languages designed to let you talk easily about lots of things that happen at the same time -- which is what happens in hardware. VHDL borrows a lot from Ada; if you know Ada then VHDL will look somewhat familiar. It originated in the US DoD. Verilog appears to be originally a commercial product. At this point, there are lots of implementations of both, and both are in wide use. I only know (some) VHDL, so I can't really comment on similarities, differences, and plus/minuses. One key thing in hardware is that you have "signals" which change as a result of some input event, and that change is visible at a later time. But not immediately. This can be confusing if you're a programmer and used to how C or similar languages work. For example, in this C code: a = 1; b = a; a and b will both equal 1 at the end. But in the VHDL code: a <= 1; b <= a; (where a and b are signals, as indicated by the fact that signal assignment operators are used), a will show up as 1 at the end of the current cycle, and b will at that time show up with the value that a had at the start of this cycle. So this is very much NOT the same thing as the C code. But it fits hardware, where signals have to propagate and new things happen as a result of previous actions at previous points in time. VHDL and Verilog can be used to model hardware operation; they can also be used to describe hardware. These are not quite the same. A model can, for example, talk about actual delays. A hardware description does not; such a "synthesizable" model is a subset of the full language. This is a common way to design what goes into an FPGA. A hardware model can be used to replicate what old hardware did; for example, I have a partial CDC 6600 model that shows how it boots, and that model includes propagation delays on some signals (which are critical to correct operation in certain spots). Reverse engineering a design into VHDL or Verilog is just like reverse engineering a program into C. Both can be very hard if you don't have much information. For example, if all you have is a complex IC spec sheet, it is likely to be rather difficult. If you have internals, it becomes more feasible. There are plenty of textbooks on the topic. I would recommend the (large) book by Peter Ashenden on VHDL. He also has a book on Verilog; given how he treated VHDL I expect that one is good too but I don't have it. paul