PDP-11/70 progress (and a cry for help)

On Tue, Feb 16, 2021 at 5:08 PM Fritz Mueller via cctalk < cctalk at classiccmp.org> wrote: I hooked the LA up to the two PROM bits that select the AMX input (RACC UAMX00 H and RACC UAMX01 H), on the ROM & Address Control board. These come from the PROM at U101 and go through a 74S174 at E97 before heading over to the DAP board. And during FET.00 we have: Addr PCB PCA AMX 260 44 44 0 "0" here selects DR (Destination Register) input to the mux and is incorrect; it should be 1 (PCB). During a single-instruction-step run, this value reads out OK on the analyzer. I noted a few other discrepancies in the capture (all of which match the ucode listing during a single-instruction step) which makes me think that the high outputs of the PROM are right on the bleeding-edge of acceptable TTL. I checked out the signal on the scope while running a BR .-1 instruction (which also doesn't execute correctly but at least doesn't halt... I don't have a storage scope to capture this during a single instruction execution) and it looks like the voltage swing is from about 0.15V to 1.7V or so. On the off chance it was the 74S174 at E97 pulling the signals down, I socketed it and substituted a spare '174 in; no change. I also noted that the +5V at this chip was about 4.95V, I goosed it up to 5.10V to see if it made a difference (it did not.) So it seems likely it's the PROM. Looks like I may have some typing to do, though given that the ROM works well enough at slow speeds I might be able to dump it with my Data I/O Model 29 and compare it against the listings in the engineering drawings, to save some time... I'll try to dump the PROM tomorrow and see what I get. - Josh