Reproducing old machines with newer technology

On 07/14/2015 10:55 AM, Noel Chiappa wrote: There are more than a few folks who call the CDC 6000 one of the first RISC machines. In particular, the 6600 with its instruction scheduling and reservation control, multiple functional units, instruction cache, etc. was quite noteworthy. You could easily recognize the earmarks of a very different machine of the time. The issues that arose when programming later RISC CPUs made me feel that I was back in familiar territory. 3-address architecture, 60 bit ones complement words, with separate sets of registers for addresses and indexing. A typical beginning programmer's problem was to write a CPU loop to move non-overlapping fields of words in the shortest amount of time (ECS not available). The best solution usually involved two words per iteration, with one instruction issue per cycle; bottom of the loop load (to overlap the branch) and top-of-the-loop store. Another challenge was to write a routine that could load and store the values of all registers from and to memory. Not as simple as it sounds. For me, one distinguishing feature is that there is no condition code register. You could branch on a register value being signed or zero, or compare and branch on the values of two index registers. Thus, the result of an operation was covered by the regular register reservation rules. The I/O processors (PPUs) had access to all of CPU memory and essentially were their own world, using a 12-bit instruction set derived from the 160A. One could also say that the PPUs were only one machine with memory and registers being time-multiplexed to simulate 10 machines. --Chuck