22 Apr
2016
22 Apr
'16
11:42 p.m.
It was thus said that the Great Eric Smith once stated:
On Fri, Apr 22, 2016 at 9:29 PM, Sean Conner <spc
at conman.org> wrote:
Hmm ... I might have been misremembering. I just checked the book I have
on the MIPS, and yes, the supervisor stuff is different between the R2000,
R3000, R4000 and R6000. Also, the R2000, R3000 and R6000 have a five stage
pipeline, and the R4000 has an eight stage pipeline.
One major problem with adding a faster CPU to
an SGI is the MIPS chip
itself---code compiled for one MIPS CPU (say, the R3000) won't run on
another MIPS CPU (say, the R4400) due to the differences in the pipeline.
MIPS compilers were specific for a chip because such details were not hidden
in the CPU itself, but left to the compiler to deal with.
Having written a bunch of R3000 and R4000/4200/4300/4400/4600 assembly
code in the 1990s, my (possibly faulty) recollection disagrees with
you. There are differences in supervisor-mode programming, but I don't
recall any issues with running 32-bit user-mode R3000 code on any
R4xxx. The programmer-visible pipelline behavior (e.g., branch delay
slots) were the same. That's only considering the CPU itself, which I
used as an embedded
processor; I never used IRIX so I don't know whether IRIX on R4xxx
might have somehow prevented use of IRIX R3xxx binaries (e.g., by
different system call conventions or the like).
That I do not know. There were very few SGIs on campus at the time.
-spc