11 Jun
2019
11 Jun
'19
noon
On 6/11/19 11:40 AM, Paul Berger via cctalk wrote:
Well in this case I have Mr Duell's schematic to go by to determine what
is input an what is output.? For the 16L8 tristate is an available
output option that you would need to specify in PLD design and I believe
can be selected individually for each output.? In the case of this HAL
it would seem likely that pin 11 tristates all outputs but output 0 at
least when pin 11 is low the output from all the rest is high but I did
not test for tristate as it does not matter in this case since pin 11 is
permanently tied high.
That's nice; but in my case, I was sent a couple of PALs to clone
without a hint of their origin. So the PAL was essentially a black box
and the task was to come up with a box that behaved similarly.
--Chuck