Ensor wrote:
Hi,
> OTOH At the company I worked for at the time,
the beige "wedge
>shaped" PSUs were dropping like flies - we found them to be
>HORRENDOUSLY unreliable....
pics? I'm not sure I recall a wedge-shaped
PSU.
OK, look here:
http://jope.fi/cbm/cbm/c64psu.jpg.
The PSU I'm referring to is the leftmost one of the three in that
picture; I've always called them "wedge shaped", but I suppose "cheese
block" would be closer to the mark, LOL.
Wow, never seen anything like that.
The ones on the right and middle
are all I know as PSUs. Ya learn something new every day.
Thinking about it, I don't think the paddle inputs weren't "real"
analogue inputs. Rather they timed how long a capacitor took to charge
through the pot inside the paddle controller.
Same for the SID. (And, I suspect
the VIC-I paddle inputs on the VIC-20).
Years later, the C64 Mouse used the paddles inputs to represent X and Y
digital coordinates via a very ingenious method, IMHO. The SID ADC
works in 512 cycle periods, clamping the internal cap to ground for 256
cycles, and then unclamping, watching how many cycles it takes to charge
the cap. The faster the charge, the lower the number. The mouse ASIC
would start up feeding +5v to the paddle line through some small
resistance, watch for the line to drop to GND, and then start timing,
turning off the 5V. At count 256, if would then start counting to a
certain position, and then bring the line to 5v. The position was time
period 256+desired value, as I recall. The value was ((6 bits of
counter mod 64) * 2). On reception, you stripped bit 0 and bit 7, and
you had the counter.
A few years ago, based on this reverse engineering some CBM folks had
done a few years back to create a mouse interface for the 64, I
implemented some AVR code to do it all in the AVR, and support the full
range of ADC values. Commodore's solution had a fixed 1MHz crystal, so
bit 0 jittered, as the timing was just a bit off (PAL units run a bit
below 1MHz, while US ones run a bit over.). The AVR code switches into
internal oscillator mode and then trims the oscillator trim register in
real time to sync with the 512 cycle clamp event.
Jim