15 Jan
2011
15 Jan
'11
9:27 a.m.
Tony Duell wrote:
I don;t know abotu the OEM manual becuase I don't have it, but I would
assume it was in there. The service manual, which I do have, says :
'In order to be valid, step pulses must be at one of two rates. I nthe
normal mode there will be 1.1 msec or more time delay between incoming
step pulses. In the buffered mode, there will be less than 350 $\mu$sec
time delay betwene them. If step pulses are incoming 600 $\mu$sec apart
for exmaple, then every other pulse would be lost causing the heads to
move only half the required number of tracks. The reason for this is that
the stap count timer locatad at positon 1A which counts down to zero in
apporoximately 500 $\mu$secwould output a low pulse. This pulse then
clocks chip 5B blocking out incoming step pulses for another 500 $\mu$sec
while cjip 1A once again counts down to zero generating a single track
step and a SEEK COMPLETE signal. At this time another step pulse is
allowed to enter, but the precious one was lost.'
-tony
For pure bad deisgn, nothing beats the Shugart
SA4000 hard disk,
IMHO. On
that thing, you can eitehr send the step pulses
one at a time, waiting
for hte 'on cylinder; signal to go active after each one. Or you can
send
a burdt sufficiently fast that the drive will
buffer them, then move the
head and assert 'on cylinder' when it's done. But if you send the burst
of sstep pulses too _slowly_, the drive wil lget confusedand end up o
nthe worng cyulinder.
That's definitely less than ideal, but if they documented the minimum
burst rate in the OEM manual, an engineer designing a controller for it
I would not have had any serious complaint.