14 Nov
2005
14 Nov
'05
11:53 p.m.
Don North wrote:
Doing some math, 2GHz/100KHz is 2000MHz/0.1MHz or
20,000. At 6X the
cycle count is then 20K/6 = 3333 (not 3.3M).
One would think it takes well less than 3000 X86 instructions to emulate
a PDP-8 instruction (assuming one instr per clock).
eh, what is three orders of magnitude between friends. :-(
nevertheless, the point was there are thousands and thousands of cycles at 2 GHz
to do a straight-forward interepreter. the ratio of host to emulated
instructions I used for my AVR estimate was 200-400 per emulated instruction,
which is probably overkill because if you are using an AVR, you are also
probably hand coding things, so the count doesn't have to be nearly so high.