29 Jun
2007
29 Jun
'07
1:08 a.m.
Dave McGuire wrote:
On Jun 28, 2007, at 6:52 PM, Chuck Guzis wrote:
(I haven't studied such systems in excessive detail, but here's my
understanding, FWIW.)
Every core, more or less, has it's own clock-phase winding, so it's like
many/most of the gates in the system have a clock input.
The clock phases are what actually cause (not just trigger) the cores to flip
state (depending on the state (current flow) in other windings on the core),
so the clock phases are a major (principle?/only?) source of energy to the
logic network, in contrast to conventional logic where the DC supplies
(B+,Vcc,Vss,Vdd,..) are the principle energy source.
Core logic is quite a different form of gate implementation than what we
normally deal with, the static state of the network is represented by the
magnetic field of the cores (not by DC voltage levels at gate outputs) and it
requires AC activity into the cores to propagate changes through the network.
The "solid state" refers not to
transistors (which were used mostly
to drive indicator lamps), but rather to the magnetic cores used not
for memory, but for logical operations; one clock cycle per core.
The master clock was driven with 6 4X150 power tetrodes.
Very unusual--and very reliable for its day.
4X150s...Are you serious? I've used ham radio transmitting
amplifiers built around those tubes. Why on earth would they need
that much power to drive the clock lines? Were their circuit
impedances that low?