1 Apr
2022
1 Apr
'22
11:51 a.m.
On Apr 1, 2022, at 2:38 PM, Brent Hilpert via cctalk
<cctalk at classiccmp.org> wrote:
On 2022-Apr-01, at 6:02 AM, Paul Koning via cctalk wrote:
I wonder if the sense wire was used as inhibit during write cycles -- that seems doable.
It would make the core plane simpler at the expense of more complex electronics. With
that approach, you have regular memory, not limited to 1 bit words.
When I looked at that ebay listing of "glass
memory" it pointed me to another item, https://www.ebay.com/itm/265623663142 --
described as "core rope memory". Obviously it isn't -- it's
conventional core RAM. Interestingly enough, it seems to be three-wire memory (no inhibit
line that I can see). It looks to be in decent shape. No manufacturer marks, and
"GC-6" doesn't ring any bells.
Well, it would still work for 1-bit-wide words, so to speak. One wonders what the
application was. There are a couple of Soviet core-rope memories up
right now:
https://www.ebay.com/itm/294558261336
https://www.ebay.com/itm/294851032351
Neat looking stuff. It doesn't look like core rope memory in the sense of the AGC
ROM, nor in the sense of the Electrologica X1. It looks more like the transformer memory
used in Wang calculators that you documented in your core ROM paper.
paul