24 Nov
2009
24 Nov
'09
9:07 a.m.
On Nov 24, 2009, at 8:38 AM, Sridhar Ayengar wrote:
Dave McGuire wrote:
Because the processor is still driving the bus. The /WAIT pin isn't
the right way to do it either. There's a DMA request pin (forgot the
name at the moment) that will cause the processor to relinquish
control of the bus. That will allow you to "halt" it and read/write
memory from the front panel (hey look a DMA front panel!). This is
what I did (mumble) years ago. I'd have to go back and dig out the
designs (I still have them some place). As I recall, to start at a
particular address, it jammed a jump instruction (and address) on to
the bus.
Single stepping *was* done with the /WAIT pin.
Doing this with anything much later than 486 is nigh impossible (and
even that is problematic) without *a lot* of seriously designed HW.
The buses are fast and have special signaling requirements (GTL, GTL+,
etc). Don't even think about modern (last 5 or so years) x86 CPUs.
In some of our labs we have bus analyzers that plug into the bus
(can't do it with the new Nehalem CPUs). Those are $500K+ each (and
are only good for that type of CPU) and each time I look at them, I'm
amazed they work as well as they do.
TTFN - Guy
On Nov 24, 2009, at 10:24 AM, William Donzelli
wrote:
If I recall correctly, its registers are dynamic, so you've gotta
keep
the clock running. On the Z80, you can single-step the CPU without
stopping the clock by using the /WAIT pin and a flip-flop driven from
/M1. I'd imagine it'd be possible to do a similar trick on the 8088.
Why not just pad out the wait times with nops? Can
modern processors be single-stepped?
Can even an 8088 be single stepped?