pdp-8/i ECO history?

Does anyone have the ECO history of the pdp-8/i available? I am looking at http://www.bitsavers.org/pdf/dec/pdp8/pdp8i/PDP8-I_CPU_blueprints_1969.pdf. On sheet d-bs-8i-0-6 there's a gate added at D6 in the drawing, probably in ECO #13, #25, or #50. It uses the M113 at F32N2 to invert something called "IO PC LOAD", and connects to a previously tied high input of the 4-input NAND at E32E2 (which calculates "PC LOAD"). The problem is, nothing anywhere in the drawings appears to generate a signal called "IO PC LOAD". I don't imagine anyone knows off the top of their head what this signal is, how it is generated. A look at the ECO history should help explain when this was added and why, though. Also, if anyone knows of an I/O device or option for the 8/i that would load a new value into the PC, that might give some clues where to look. Thanks in advance, Vince (I am making excellent headway on a project which translate the 8/i schematics, including all the options, into Verilog for an FPGA, but I currently have this signal tied to an input pin for lack of any information about it.) -- o< The ASCII Ribbon Campaign Against HTML Email!