26 Aug
2014
26 Aug
'14
5:36 p.m.
On 2014-Aug-26, at 3:27 PM, Eric Smith wrote:
On Tue, Aug 26, 2014 at 2:46 PM, Tony Duell <ard at
p850ug1.demon.co.uk> wrote:
Here's a quote from TI, mentioning the same 5.5V extreme as Fairchild, but not
providing the explanation:
Something about supply line spikes causing
breakdown of the input
transistor.
I've heard that explanation and I suppose it sounds plausible but I would like
to find an authoritative statement from TI (i.e., in a TI data sheet
or application
note). From "TTL Integrated Circuits Catalog from Texas
Instruments" / 1 Aug 1969:
"Unused inputs of AND and NAND gates and unused preset and clear inputs of
flip-flops:
Tie directly to +Vcc where Vcc is guaranteed to *always* be <=
5.5V; (emphasis TI's)
or
Tie to Vcc through resistor >= 1Kohms. Several unused inputs
may be tied to one resistor;
or
Tie to unused input of same gate if maximum fan-out of driving
device will not be exceeded;
or
Tie to unused gate output where unused gate input is grounded.
"