I wrote:
> You want the book "The Apple II Circuit
Description", or "The Apple IIe
> Circuit Description", by Winston Gayler.
Sellam wrote:
While that's a good book, it has nothing on the
disk controller. See
my previous message for a better selection.
Oh. I suppose I must be hallucinating when I look at this copy in
front of me. The table of contents lists chapter 9 as being "The
Disk Controller". And pages 9-1 through 9-45 seem to give a detailed
explanation of how it works. But I guess this must just be a
particularly strange side effect of the drugs that I'm not taking.
> The bits shift in from the right, and there's
no counter. The only
> way you can tell that the complete "nybble" has been read is that the
> MSB of the shift register is set.
How...lame. There's a specific number of cycles
that it takes to assemble
an 8-bit byte.
No, there aren't. The disk drive operates asynchronously to the
computer, and motor speed variations of both the drive that wrote the
disk and the drive that's reading it affect it a lot.
Why can't one just go off this timing to determine
when a
full byte is read? And if this is possible, then does that mean that one
can really store a byte that doesn't have the MSB set, and subsequently
read it back?
Not reliably.
I see. And this is where I'm confused. Beneath
Apple DOS shows diagrams
that indicate there's a clock pulse between every data bit. So either
that diagram is wrong, and there are no clock pulses,
The authors of Beneath Apple DOS had no clue whatsoever as to what was
going on at that level, so they apparently just assumed that it worked
the same as other disk controllers in that regard.
There are no clock bits. That's the whole point of GCR.
Fortunately they understood the higher-level stuff, so the rest of
the book is much more accurate.
According to my reading (in Beneath Apple DOS), you
can only have *one
pair* of consecutive zeros in any one byte, but it was not clear if that
was a hardware constraint or an artificial constraint to pare down the
number of "legal" values.
Artificial constraint. The hardware (w/ the 16 sector state machine)
can deal with any nybble that has the MSB set, and no more than two
consecutive zeros.
Eric