27 Jun
2010
27 Jun
'10
11:26 a.m.
"Walter F.J. Mueller" <w.f.j.mueller at gsi.de> wrote:
True. But you cannot run almost anything else. I don't think I've seen
any other language that do not require the FPP.
True. Definitely will not break anything. But it will make your life
more complicated. :-)
Johnny Billquist <bqt at softjar.se> wrote:
Yes, I know of these systems. However, that is not an 11/74 on that
picture, but an 11/70mP. There is a difference...
As pointed out, the 11/70mP was marketed as an 11/74, but it's a
different CPU.
The easiest way to see that this is a picture of an 11/70mP is by
looking at the lower rotary switch, which only have four positions, and
not eight (which the 11/74 have). So no CIS on this machine.
The only 11/74 picture I've seen so far is the silk screen panel picture
posted a few days ago. Unfortunately I've already forgotten the name
(I'm lousy with names, sorry) of the person who posted it, and who also
worked on the 11/74 CIS microcode.
The machine on that picture is probably CASTOR:: by the way.
I wasn't aware that any prototypes ever were
produced and came as
far as being functional. I thought it was just paper work that
had bee done.
The 11/74 wasn't marketed, as pointed out in this thread, but a
few systems were build by DEC. A picture of such 11/74 system
was made available by Tim Shoppa, see
http://www.trailing-edge.com/~shoppa/1174Xopen.jpg
You'll nicely see the four CPUs. 
arcarlini at iee.org wrote:
Yes, when you run multiple CPU configurations, you do get many flat cables.
However, if you were to run the 11/74 in a single CPU configuration, it
would not have had more flat cables than an 11/70. So it seems strange
if that would have been the reason for cancelling it.
On the other hand, I think that CIS never was popular, or in any demand,
for the PDP-11, so if that (and multiprocess capability) was the only
things the 11/74 brought to the table to differ it from tne 11/70, then
I can understand why they would cancel it if they had problems with the
multiprocessor part.
I've read somewhere that it [PDP-11/74] was
full of flat ribbon
cables and would have been a beast to maintain.
Well, you see on the picture that there was quite a bit of
flat ribbon cables :). The 'PDP 11/70 Multiprocessor Technical Manual
(Preliminary Version)'
is on bitsavers, see
http://www.bitsavers.org/pdf/dec/pdp11/1174/EK-70MP-TM_PRE_1170mp_Prelim_Te…
and gives you a feeling of the modules and interconnects.
Yes. And all evidence I ever see is that the only systems DEC actually
did get working was the 11/70mP. That they actually got the 11/74 (CPU)
beyond paperwork was what was news to me.
Johnny Billquist <bqt at softjar.se> wrote
That would be nice. While RSX don't use it, you could use it for Unix,
or other systems.
The J11 also have the cache bypass bit in the PDR, btw.
What instructions are you thinking about when you say 11/34 btw?
You do know that the J11 is already designed for
mP usage, except that
DECs testing of that was even more secret than the 11/74?
Sure, the mP instructions WRTLCK and the TSTSET of the J11 are
documented, and allow cleaner way to implement spin locks than
the 'asrb hack' of the 11/74. In a future version of the w11a I'll
probably also implement the instructions supported by 11/34 and
J11 and make the 'processor profile' selectable at start time, much
like in the simh simulator. But FPP is
among the most important things in there as well, I'd say.
Lots of software who won't be happy without it.
That's true from a performance point of view. However
- you can run RSX and Fortran without FPP (did this 30 years ago
when the FPP broke on the 11/45 I was working with...). - you can run 2.11BSD without FPP (I'm doing
that each time I
boot 2.11BSD).
Yes, that was fixed recently, right?
So a FPP is very good to have, but not my highest
priority. Also,
it's quite a project to design, implement and verify it, with the
verification, as usual, being the most time consuming part.
True.
By the way.
You don't have to worry about cache coherency. The
PDP-11/74 do not do that. Cache coherency is managed by software
on the PDP-11 (well, in RSX, since that's the only system that
supports the hardware). In short, the real hardware do not implement
any sort of cache coherency in hardware.
I know, but I'll go for a cache with full cache coherency. That will
make it a lot easier to try a MP hack for 2.11BSD. And RSX, if I ever
get to it, will not mind. Johnny Billquist <bqt at softjar.se> wrote:
Hmm, I seem to remember checking numbers a while ago and came to the
conclusion that if the 11/70 would have all memory as cache, it would
outperform the J11. Atleast at 18MHz, maybe also 20MHz.
(Btw, that table is slightly wrong, as the 11/9x eventually made it to
20MHz).
I have a processor handbook which gives instruction speeds of 11/70
instructions with cache hits and without, which tells you how fast the
machine would be if you were all cache. The 11/70 suffers because memory
is so slow.
Johnny
Good thinking.
But I'm surprised by some numbers here. The J11 at 20 MHz is
only slightly faster than an 11/70. In fact, if you can throw
the 11/70 into running all from cache, it might even be slightly
faster than an 11/9x.
Or so I seem to remember from looking at the numbers back when
I last was digging into this.
Maybe I'm mixing some numbers up here... What I do remember for
sure is that the 11/9x machines run at 20 MHz, and that they are
not more than maybe 1.2 times the speed of an 11/70 in general.
oops, you are right, I was mixing numbers here and forgot about
a factor of four. Here the revised arguments:
See http://www.village.org/pdp11/faq.pages/prfmnc.html , there
is a table comparing 11/70 with various J11 systems:
11/23 11/53 11/73 11/83 11/93
----- ----- ----- ----- -----
CPU F-11 J-11 J-11 J-11 J-11
Microcycle(ns) 300 267 267 222 222
Clock (MHz) ? 15 15 18 18
Performance 0.2 0.5 0.7 1.2 1.4
(11/70 = 1)
Cache no no yes yes no
Floating-Pt opt no no yes yes
Coprocessor
My mistake was to forget that the J11 needs 4 clock cycles per
microcycle (MC), that's why 18 MHz clock leads to 222 ns MC period.
In the end the J11 (222ns MC) is faster than the 11/70 (150 ns MC)
because it has a better micro architecture (three stage pipeline
vs. instruction prefetch only). The J11 is roughly a factor two
better compared to 11/70 in terms of MC efficiency.