27 Jan
2014
27 Jan
'14
12:30 p.m.
The problem is
to get IORQ/, M1/, Rd/ etc right -- and the right clock
pulses on ne phi. IRIC, it does a write if it sees IORQ/ and doesn't see
Rd/ or M!/ within a given number of clocks, it then samples the data bus
after said number of clocks. Tryign to get that right on a non-Z80 is
mnot totally trivial.
Maybe not trivial but it is doable. Sometimes you have to build an
Sequencer to get the timings to fit. IORQ just distinguishes between memory and IO Access,
it is possible
to do memory mapping with those chips.
Well, obviousklly you can arrange for the chip to be accessed as
memory.But if you simply sonnect IORQ/ of the SIO to MREQ/ of a Z80 it will
not work. FOr one thing it will think every instruciton fetch is an
interrupt acknowledge.
-tony