5 Sep
2007
5 Sep
'07
8:16 p.m.
Dave McGuire said:
It's worth noting that some CPLD families are
more-or-less direct
implementations of common PAL architectures. A Xilinx XC9536 CPLD,
for example, is very similar to two of what might have been called
PAL36V18. This comes in very handy if you're experienced with PAL
design and want to move into higher-density devices.
Nah, while you can use ABEL and PALASM scripts to convert into programming
patterns for a CPLD, you can't vice versa map Verilog and VHDL
descriptions of certain complexity into PALs/GALs. It is not the gate
count alone that counts, but at that point the flexibility of the
interconnection network between the logic blocks. A difficulty with
GAL/PALs is that their logic blocks typically contain a flipflop whose
output is more or less directly associated with an output pin of the chip.
You can feed it back to the input and/or matrix to build Moore-style
finite state machines, but you usually lose an output pin for those hidden
feedbacks. CPLDs in contrast separate logic blocks an I/O blocks and allow
almost free assignment between logic and I/O.
Regards
--
Holger