see below, plz.
Dick
----- Original Message -----
From: "Chuck McManis" <cmcmanis(a)mcmanis.com>
To: <classiccmp(a)classiccmp.org>
Sent: Wednesday, October 31, 2001 9:55 AM
Subject: Re: CPU design at the gate level
At 08:15 AM 10/31/01, Ben wrote:
That is true there is baggage.My two gripes today
are
1) No bootstrapping a minimal system in hardware & software - you need
everything to run.
Take a page from Classic computers as I did and put a dedicated "console
processor" on the front of your FPGA. I've got a board for doing a
"soft"
robot CPU that I hope to get to after BattleBots that has a PIC chip (small
single chip MCU) as the console processor. It loads the main CPU from
either serial EEPROM or from a serial line into the FPGA on power up,
sequences the power, and provides the diagnostic interface when things go
strangely.
This is too technical an approach, even for today's engineers. People want
the
"thing" to run when they put in the batteries.
2) Non serviceable equipment and docs.
That's because there's nothing to service and nobody to do it. Forget the
doc's. Today's engineering grad's know just which buttons to push, but
can't
read and write. It's a skill set that died over the past generation. When was
the last time you got a manual that told you anything with a piece of hardware?
This is truly a pain.
--Chuck