18 Dec
2008
18 Dec
'08
10:03 p.m.
Ben,
Sometime late January, I hope to have the logic for a
20 bit cpu using 5
CPLD's,
I find them a little more DIY freindly than FPGA's. Expect to have
ballpark PDP-8/e
speeds with but I have run with .8 us static ram memory cycle because I
can't use
the trick the PDP-8 uses for address generation, but run address generation
thru the main adder. That is the price you pay for modern features like
a Stack pointer
or Index register.
No. That's the price for using arrays of CPLDs.
In an FPGA you get waste amounts of logic and very fast RAM. The only hassle is soldering
FPGAs.
But cheap development boards can be found.
The fun part here is just having I/O pins just to
display the AC, Mar and data
from the last memory cycle, and a Switch register. Good luck with your
design
on those features.
Where's the problem? I currently use a VGA front panel (view
only) to see what my "machine" is doing :-)
So everybody else can do that, too - on an FPGA, of course :-)
Apropos "main adder": one thing about my PDP-8 design: It is designed for speed,
not for size. So
there are a lot of
adders - no adder will get it's input switched. I always have a PC+1, PC+2, AC+1,
MD+1, etc.
Results are selected by multiplexers.
Philipp
--
http://www.hachti.de