1 Oct
2010
1 Oct
'10
6:37 p.m.
--- On Fri, 10/1/10, Chuck Guzis <cclist at sydex.com> wrote:
I can't seem to derive a stable expression
(Verilog) for
adding two
numbers, A and B,in ones' complement without computing A+B
and A+B+1
as a two's complement adder and then selecting one or the
other
result depending on the carry-out.? This seems to me
to be a huge
waste of logic.
I am not sure exactly what you mean by a "stable expression", but I presume that
your difficulty is in coming up with a purely combinational formulation of the end-around
carry, suitable for execution in a single cycle, that seems suitably economical in logic.
I'm wondering if, historically, the situation was any better in hardwired logic. It
was common in those days to do carry propagation in a second cycle (minor cycle, clock
phase). This allowed such tricks as using a gated toggle input on the accumulator
flip-flops as an XOR/accumulate, to implement the XOR part of a half-adder. This was even
done for 2's complement.
--Bill