the 100ua only applies to the 74L family and it only represents the high logic level
current that it will supply into other logic inputs. One of the key design specs for TTL
was the input current to guarantee a specific logic level. For normal TTL, TI specs call
for -1.6ma for a logic low and 40ua for a logic high (these are input currents). In other
words, ten standard TTL loads for both low and high logic levels. Ten was the usual output
capability of TTL outputs.
Short circuit current is spec'd too and at a minimum, is 18ma for a TTL output that is
high.
You can find the standard logic currents on page 1076 of the 2nd edition on bitsavers and
the short circuit current on the same page. Of note, the 18ma was only the minimum short
circuit current, TI spec's 55ma for the maximum. It also states that you should not
short more than one output at a time. Frankly, as I said before, shorting anything for any
amount of time is a great way to create noise transients.
I have tried to never recall anything from memory anymore on this list because there is
always someone who disagrees...
best regards, Steve Thatcher
-----Original Message-----
From: "Dwight K. Elvey" <dwight.elvey(a)amd.com>
Sent: Jan 10, 2005 3:46 PM
To: cctalk(a)classiccmp.org
Subject: Re: RTL Logic
Hi
The 16ma is for sink of the NPN to ground. The pullup
is limited to around 100ua as I recall.
Dwight
From: "Steve Thatcher"
<melamy(a)earthlink.net>
well, I design by specifications. The TI specs say that the short circuit
current
for 74xx series is 18ma which is also not within specs for the general
output current capability of 16 ma. Transient shorts like this are a great way
to generate power supply noise. I guess I never applied any type of "preliminary
hackery" to systems I have developed.
-----Original Message-----
From: der Mouse <mouse(a)rodents.montreal.qc.ca>
Sent: Jan 9, 2005 5:15 AM
To: cctalk(a)classiccmp.org
Subject: Re: RTL Logic
Except that totem-pole outputs usually have just a transistor to
ground, but a transistor and resistor to Vcc. This means that the one
driving the signal low will win, and, provided not too many outputs are
wired together, it will sink the current without damage. (I've
actually built circuits that depended on this, though I've never liked
it and never considered it suitable for more than preliminary hackery.
I've also always never done it for anything where the conflict will
last more than nanoseconds, as when building an ~R/~S flip-flop out of
two cross-coupled inverters rather than the more usual NANDs or NORs.)