FPGAs, unobtanium and FPJ11s

Roger Ivie wrote: I think you're confusing this with 11/23, or maybe 11/40 options. There is a microcode ROM for the 11/03, which contains EIS/FIS (ie, both the Extended Instruction Set and the Floating Instruction Set). It's called KEV11, not FIS-11. There is a FIS option (and a separate EIS option) for an 11/40. However, the FIS is not the same as other PDP-11 floating point instructions. For a start, it's all stack-based (no register operations) and it uses a different floating point format. Which is why the opcodes are different too. There's a similarly-named option called KEF11 for an 11/23, which does implement the normal PDP-11 floating point instructions (in microcode). It needs the MMU present, because it uses registers in the MMU; it doesn't implement EIS because the basic 11/23 KDF-11 chipset already has EIS, unlike the KD-11 chipset in the 11/03. It doesn't implement FIS either, because there's no point. There is also a quad board with a floating point processor which plugs into an 11/23 (or 11/24) instead of the KEF-11; this is called an FPF-11, and it doesn't need the MMU registers because it has its own. I've never heard of an FPP-11. There are several FP11-x boards for Unibus machines. There's no CIS for an 11/03; there is a CIS option for KDF-11 machines, which consists of a carrier that plugs into a *pair* of microm sockets on an 11/23 or 11/24. The carrier holds six chips. There's also a CIS for the 11/44 (two board set). Yes, that's a KUV-11, M8018. I suppose if you could fit the floating point instruction set into 1024 microcode words, you'd almost be able to implement floating point -- but there would still be no registers available to operate on. -- Pete Peter Turnbull Network Manager University of York