From: "Allison" <ajp166 at
bellatlantic.net>
Subject: Re: Floppy controller questions
From: Philip Pemberton <philpem at dsl.pipex.com>
Date: Wed, 24 Aug 2005 00:46:29 +0100
To: cctalk at
classiccmp.org
In message <m1E7h9n-000IyXC at p850ug1>
ard at p850ug1.demon.co.uk (Tony Duell) wrote:
Also be aware that many HD-capcable 5.25"
drives turn at 360 rpm all the
time. Which means the data rate if you put a DD (or for that matter an
SD) disk in them is 6/5 times what you'd get with that disk in a DD drive
(which turns at 300 rpm). You may well need to provide a suitable clock
for 300 kbps, for example.
Ick. Time to find a 24MHz crystal oscillator :-/
Divide by 3 gives 8MHz, div24 for 1MHz, div48 for 500kHz, div96 for 250kHz.
And none of those are powers of two. Yay. I think I'll just stick to 8MHz and
1M/500k write clocks.
Unless you use a drive that spins faster then the 500khz rate is fine.
I still need to deal with the "only 16uS to
grab a byte of data" issue.
That's going to be a major pain when the CPU is running at 2MHz... Thankfully
IDE/ATA is fairly speed independent.
I suppose I could use interrupt mode, and hijack the INT (or maybe the NMI)
vector whenever the FDD is being accessed.
Yep, remember the worst case for "fast is 13us! I'd plan for that.
Also the slow rates will give you nominal 32us (27us worst case).
>Isn't learning fun?
---snip---
Hi
One thing to consider is that you can unroll the loop and just
fetch or write data and increment the pointer. Even on an
8080, this is reasonably fast. If you know the speed of the
processor and the speed of the controller, you don't have to
check the data ready bit every time. You just need to do it
often enough to resync things. Another trick, if you are
using a loop, is that you can make the loop partially unrolled.
You only modify the counter once every few data read or writes.
You do, say, 4 bytes at a time. Any odd amounts needed can
be unrolled.
Using any one of these tricks will get you in the range.
On a PC, the main issue is that you need to shut down all
interrupts and be aware of refresh if it uses memory cycles.
On a processor that I was playing with, I found that the
processor was too fast for the FDC chip. It was only
running a 4 MHz instruction speed.
Dwight