26 Jan
2006
26 Jan
'06
5:59 a.m.
Allright, I had a look at the schematics during the lunchbreak
to prepare for some measurements this evening. Let me know if
my conclusions from a look at the schematics are ok, so far.
Stage 1, from the Wirelist at the start of the printset, we see that BUS
D15 goes to slot 8 (the M7900 Unibus Interface) and to no other boards in
the controller. The other pins listed for this run are for the MUD/SPC
slots and the Unibus In/Out connectors.
On page 'M7900 UNIBUS INTERFACE (UB7)' the databus bit 15 is
connected to the tranceiver 8641 (E10) pin 15.
Yes, with you so far.
If pin 9 (UB7 ENA DATA DRVRS L) is '0', input
pin 14 appears
inverted at the pin 15.
Yes, and note that that input (pin 14) is driven by tri-state drivers all
over the place!). It goes onto the backplane and seems to go to all the
other cards. And it can be driven on the Unibus Interface board (sheet
UB5, output of E16d (pin 12 of E16, a 74LS257).
As the diagnostic says that it expects 000200 on reading CS1,
and the result is 100200, you can say 2 things:
1) 'problem' with data bit 15 (where ever)
2) as the signal "UB 7 ENA DATA DRVRS L" is common to E3, E10,
E11, E2, and E1 that signal must (?) be OK, because that
signal enables all other databus bits, which seem OK.
So, either E10 (in #14, out #15) is defective, or the problem
is already with the signal driving pin 14 ("TS REG BUS 15 H").
Let's look at E16 (sheet UB5). That mux is concerned with reading the
CSR1 (the register where the diagnostics first found a problem) and the
BA (Bus Address) register. I think of it as 3 posibilities
1) The bus driver is defective and always outputing a low (==1 on the
Unibus). Unlikely becuase it's clearly not _stuck_ low, or the machine
could never work at all. It would mess up memory reads, etc
2) The address decoding logic, or E16, is defective, and we're not
actually reading the UB5 CONTR ERROR H signal on that bit. But it appears
we are reading the right values for the other bits in that register, so
this is unlikely too (much of the logic is common to all bits, after all).
3) UB5 CONTR ERROR H is actually a logic 1 (high). This would be easy to
check with a logic probe.
It comes from E46a (also on sheet UB5), a 7474 D-type. It's used here as
an SR flip-flop. It's cleared by the UB1 CONTR CLR L signal (which is
what the diagnostic attemtped to assert, look at sheet UB1 to see how
that's produced), it's set by the gates around that FF on the schematic.
Note that if the SET input is held asseted (low), then UB1 CONTR CLR L
will not be able to permanently reset this bit.
So what I'd do@
1) Put a logic probe on the output of E46 and run that diagnostic. Is
that pin high all the time (ignore a possible narrow low pulse when the
thing actually tries to reset it). If not, in particular if it's low when
the diagnostic gives the error, then go forward to E16, etc.
2) If it's high, then check you do get the reset pulse on the RESET
input. Just to eliminate open PCB tracks, etc.
3) And then look at the set input. If it's sitting high, then suspect E46.
4) But if it's low, then something is trying to set that flipflop. look
at UB2 CONTR TIMOUT (1) H (high to set it), RS6 COMBINED ERROR L, CN5
COMBINED EROR L, DA3 COMBINED ERROR L, DR6 COMBINED ERROR L (each one
would set the FF if it was low), and trace back from there.
When we've found the defective signal, we can trace back further into the
logic.
-tony