DRAM camera sensor

Phase I (simple B&W): I used a Z-100 computer with a TI 256K DRAM (512 x 512). The video chip in the z-100 could be configured for 640 x 512 and the DRAM imager replaced one DRAM chip (ES) and was on a 1 foot tender (which is about the functional limit). Using a simple assembly code to read the DRAM transform the logic address to physical topology. Phase II (gray scale): more complex, used a memory board and replaced DRAM to a DRAM on tender. Programmed the DRAM controller for various refresh rates (soak time). Of course the other "bits" on the memory board were rendered useless. TI (and others) would publish a memory map to help with the topology decoding. Of course it did not directly address redundant bit lines. At 10:34 PM 6/1/2007, you wrote: