21 May
2020
21 May
'20
8:46 a.m.
Helpful tips - I agree with avoiding vendor extensions. Thanks.
I seem to recall some issues regarding edits inside vs. outside Vivado
as well, but it has been more than a year, so the recollection is fuzzy.
JRJ
On 5/21/2020 6:34 AM, Sytse van Slooten wrote:
If you?re targeting FPGA hardware (opposed to a design
for a foundry, or a design you want to run exclusively in a simulator), it is kind of
inevitable that you work with the toolchains that the hardware vendor supplies. Would be
nice if you could choose freely from competing toolchains, but the hardware isn?t exactly
open, so that?s not going to happen.
So basically what it comes down to is Quartus or Vivado. I?ve kind of implicitly chosen
Quartus, because the Altera based development boards tend to be a lot nicer and cheaper
than the Xilinx based stuff. I haven?t even followed the upgrades from ISE to Vivado.
Not sure if the level of doggyness is any different between those, it?s more like getting
to know the specific bugs and working around them. Can be pretty annoying at times though.
For instance, one of the things Quartus doesn?t get is that if source files are changed,
it might make sense to recompile - it only gets that if you change sources through its own
editor. Not really a big problem maybe, but it shows that the tools are far from
friendly.
One of the things I?ve done with my pdp11 vhdl from the start is that I?ve not used any
vendor specific constructs or language extensions. That?s probably the only design
decision that I?m still really happy about - it allows me to change to another vendor and
another tool chain at will.
Cheers
Sytse
On 21 May 2020, at 04:22, Jay Jaeger via cctalk
<cctalk at classiccmp.org> wrote:
As I wrote in my last post, but write here for use as a separate thread:
I'd be interesting in hearing from folks what toolsets they have used
for HDL (VHDL in particular). I started with Xilinx ISE and then
graduated to Vivado for later chipsets - unfortunately, Vivado seems to
be something of a dog, in terms of time to compile HDL and synthesize logic.
JRJ