Plane of core memory

The zigzag routing, you mean? Yes, that's to minimize crosstalk. It's nicely described in a training manual for the Electrologica X1. The issue is that concident current selection send a "half-current" pulse through a whole row and column of cores. While the resulting induced current in the sense lines is small per core, it isn't zero since the hysteresis curve isn't perfectly square. If all those pulses summed up, the resulting noise would swamp the signal from the selected core. The solution is to route the sense line so it passes through the cores in a zig-zag fashion. This means half the cores in a row or column generate a pulse of one polarity while the other half produce the opposite polarity. If all cores were identical you'd end up with just two cores worth of noise. They aren't all identical, of course, but it still reduces the noise enough to avoid the problem. A similar but not identical issue appears in rope core ROM. Brent Hilpert's paper on those devices shows how it was solved there (in the AGC flavor; the ELX1 does it differently). paul